Power supply for class g amplifier

ABSTRACT

A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/858,101 filed Dec. 29, 2017, and entitled “POWER SUPPLY FOR CLASS GAMPLIFIER,” which claims the benefit of U.S. Provisional PatentApplication No. 62/443,573, filed Jan. 6, 2017 and entitled “POWERSUPPLY FOR CLASS G AMPLIFIER,” the disclosure of which is incorporatedherein by reference in its entirety.

TECHNICAL FIELD

This disclosure relates to a power supply for a class G amplifierincluding a regulator and a controller configured to operate theregulator based on an input signal.

BACKGROUND

Class G amplifiers refer to the class of amplifiers that dynamicallyswitch supply voltages to improve on the amplifier's power efficiency.The Class G amplifiers are a modification of another class of amplifier(normally Class B or Class AB) to increase efficiency and reduce powerdissipation. Class G amplifiers take advantage of the fact that musicaland voice signals have a high crest factor with most of the signalcontent at lower amplitudes. Conventional Class G amplifiers usemultiple power supplies, operating from the power rail that provides theoptimum power dissipation.

A Class G amplifier uses a minimum of two different supply rails. Thedevice operates from the lower supply until a higher supply is needed.At this point the device switches the output stage to the higher supplyrail. Once the output signal drops below a predetermined level, thedevice switches back to the lower rail.

There are a number of trade-offs associated with Class G amplifiers:selecting the proper number of supplies and the voltage differencebetween the supplies to optimize at lower voltages, while minimizingpower dissipation. Two different rails minimize the complexity of thepower supplies, while providing sufficient voltage flexibility.Additional rails may reduce power dissipation further but at the cost ofhigher component count, complexity, and reliability. Another issue isthe length of time the device operates from the higher rail. Whileoperating from the higher supply rail, power dissipation increases.Switching back to the lower rail too early may result in distortion dueto clipping, while remaining at the higher rail for an extended periodof time will result in a degradation of efficiency.

Embodiments of the invention address these and other limitations in theprior art.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a block diagram of a class G amplifier systemaccording to the disclosed technology.

FIG. 2 illustrates a block diagram of the headphone regulator of FIG. 1.

FIG. 3 illustrates a more detailed block diagram of the headphoneregulator of FIG. 1.

FIG. 4 illustrates the configuration of the buck charge pump shown inFIGS. 2 and 3 for a 1.5:1 mode for a charging and a discharging phase.

FIG. 5 illustrates the configuration of the buck charge pump shown inFIGS. 2 and 3 for a 2:1 mode for a charging and a discharging phase.

FIG. 6 illustrates the configuration of the buck charge pump shown inFIGS. 2 and 3 for a 3:1 mode for a charging and a discharging phase.

FIG. 7 illustrates the configuration of the inverting charge pump shownin FIGS. 2 and 3 for a charging and discharging phase.

FIG. 8 illustrates a timing chart for an initialization of the class Gcontrol system.

FIG. 9 illustrates a timing chart for class G control signal timing ofthe class G control system.

FIG. 10 illustrates a state diagram for class G control timing of theclass G control system.

FIG. 11 illustrates a first timing diagram for class G control timingaccording to various signal conditions for the class G control system.

FIG. 12 illustrates a second timing diagram for class G control timingaccording to various signal conditions for the class G control system.

FIG. 13 illustrates a third timing diagram for class G control timingaccording to various signal conditions for the class G control system.

FIG. 14 illustrates a fourth timing diagram for class G control timingaccording to various signal conditions for the class G control system.

FIG. 15 illustrates a fifth timing diagram for class G control timingaccording to various signal conditions for the class G control system.

FIG. 16 illustrates a sixth timing diagram for class G control timingaccording to various signal conditions for the class G control system.

FIG. 17 illustrates a block diagram of the clock generation.

DETAILED DESCRIPTION

FIG. 1 illustrates a block diagram of a system of the disclosedtechnology according to some embodiments. The interpolator 100 anddigital-to-analog converter (DAC) 200 are part of a conventional audioDAC design. The output from the DAC 200 is sent to a Class G amplifier104. Active Noise Cancellation (ANC) 300 is a digital signal processingcircuit to produce a noise cancellation signal that is fed to the DAC104. Both the interpolator 100 and the ANC 300 receive an audio inputsignal, and the ANC 300 also receive an input from the interpolator 100.The output from the interpolator 100 is mixed through a summer 102 withthe output of the ANC 300 before being fed to the DAC 200.

The Class G control circuit 400 takes as an input the audio input signaland the ANC 300 output, makes decisions on the anticipated signalconditions, and outputs signals to control the Class G regulator 500,which will be discussed in more detail below. The Class G controlcircuit takes advantage of the delay through the interpolator 100 tomake decisions before the audio signal reaches the DAC 200. The Class Gregulator 500 is an analog circuit that produces the power supplyvoltages for the Class G amplifier 104. Because it takes time for theClass G regulator 500 to settle to new output voltage settings, theClass G control circuit 400 anticipates the demands on the audio powersupply voltage and builds in margins so the Class G amplifier 104 willnot clip on an insufficient supply voltage.

FIG. 2 illustrates the Class G regulator 500. The Class G regulator 500is a charge pump converter with configurable discrete output voltages.The Class G regulator 500 includes a multi-mode buck charge pump 502 andan inverting charge pump 504, each of which will be discussed in moredetail below.

FIG. 3 illustrates the Class G control system that creates a bipolarsupply for the Class G amplifier 104 from the 2.7V to 3.6V power supply(not shown). The Class G regulator 500 creates the bipolar supply fromthe input rail VDDHP using the buck charge pump 502 for a positivevoltage rail and the inverting charge pump 504 for the negative voltagerail. Both the buck charge pump 502 and the charge pump inverter 504 areunregulated, so the output circuitry should provide power supplyrejection. The Class G control circuit 400 includes a low dropoutvoltage regulator 402, a controller 404, a comparator (not shown) todetermine when the buck charge pump 402 has reached the desired value onfalling transitions, a non-overlap clock generator 406 to generate clocksignals for both the buck charge pump 502 and charge pump inverter 504,which will be discussed in more detail below.

The buck charge pump 502 uses two fly capacitors cflyp1 and cflyp2 inthree different configurations, shown in FIGS. 4-6, to implement 1.5:1,2:1, and 3:1 modes to provide discrete Class G operation, which will bediscussed in more detail below. With a nominal input voltage of 3.3V,the 1.5:1, 2:1, and 3:1 modes result in an output at VDDHP of 2.2V,1.65V, and 1.1V, respectively.

To minimize the number of switches 202 required for the different modes,switches 202 may be shared between modes where possible by selectivelycontrolling the non-overlap phase signals to the switches 202. As seenin FIGS. 4-6, the buck converter 502 includes nine switches 202 to makethe desired connections for the various modes. FIGS. 4-6 show the flycapacitors cflyp1 and cflyp2 connections during the charge phase (ϕ1)and the discharge phase (ϕ2), along with a circuit diagram indicatingwhich switches 202 are used during the two phases (marked with either ϕ1or ϕ2) to create the desired connections.

The switches 202 marked ϕ1 are closed during the charging phase, whilethe switches 202 marked ϕ2 are open during this phase. During thedischarge phase, switches 202 marked ϕ1 are open and switches marked ϕ2are closed.

FIG. 4 illustrates the configuration of the buck charge pump 502 for a1.5:1 mode, FIG. 5 illustrates the configuration of the buck charge pump502 for the 2:1 mode, and FIG. 6 illustrates the configuration of thebuck charge pump 502 for the 3:1 mode.

The charge pump inverter 504 has a configuration as shown in FIG. 7,charging the fly capacitor cflyn during the charge phase ϕ1 anddischarging the fly capacitor cflyn during the discharge phase ϕ2. Aswith FIGS. 4-6, FIG. 7 shows the fly capacitor cflyn configuration inthe charging phase ϕ1 and discharging phase ϕ2. Switches 204 marked ϕ1are closed during charging, while switches 204 marked ϕ2 are open.During discharging, switches 204 marked ϕ1 are open and switches markedϕ2 are closed.

With respect to FIGS. 4-7, the dotted switches 202 and 204 are switchesthat remain open during both the charge and discharge phase for thevarious modes.

At initialization, the Class G system generally follows the diagramshown in FIG. 8.

As discussed above, the buck converter 502 operates in three modes. Thebuck converter 502 also has four possible states: 00, 01, 11, and 10.After initialization, the buck converter 502 will be in the 00 state,which is equal to the 3:1 mode with the clock disabled. Since the ClassG mode selections are gray coded, a single mode control signal willchange during each transition. The allowable Class G mode transitionsare shown in table 1 below:

TABLE 1 Mode before Transition Transition Transition Transitiontransition to 00 to 01 to 11 to 10 00 - Clock — Increasing Not Notdisabled, Allowed Allowed 3:1 mode 01 - 3:1 mode Decreasing — IncreasingNot Allowed 11 - 2:1 mode Not Decreasing — Increasing Allowed 10 - 1.5:1mode Not Not Decreasing — Allowed Allowed

There are four control signals that are configured to initiate a Class Gmode transition, sw_gmode, gmode<1:0>, and gdir, as shown in FIG. 3.FIG. 9 illustrates a timing chart based on the four control signals. Themode transition is initiated on the rising edge of sw_gmode. Thetransitions of the control signals gmode<1.0> and gdir are nominallycoincident with the rising edge of sw_gmode. In FIG. 9, the timeinterval tsu is the set up time relative to the rising edge of sw_gmode.The time interval t_transition is the width of the positive sw_gmodesignal needed to complete a transition, while the time interval t_staticis the width of the negative sw_gmode signal needed before the nexttransition.

Mode 00 is only used for the start of the operation. The buck chargepump 502 starts in this mode to initialize and then immediatelytransitions to mode 01. Mode 01 tolerates ½ full scale signals whilemode 11 tolerates signals that are ¾ full scale. Signals higher than ¾full scale stay in state 10.

As mentioned above and shown in FIG. 9, there are two time intervals foreach mode transition. The time interval t_transition is the time thetransition signal holds high during a mode change. The time intervalt_static is the minimal time between the end of the t_transition signaland the start of the next mode change. T_transition has a specificationminimum of 150 μs and is typically 200 μs. T_static has a specificationminimum of 20 μs and typically is 1800 μs.

To avoid signal clipping, two consecutive mode increases must beperformed before the large signal hits the Class G regulator 500. Ift_transition is 200 μs and t_static is μs, such two mode increases take420 μs to complete. Therefore, the large signal must be detected 420 μsahead of time so the buck charge pump 502 has enough time to changestates. The interpolator 100 has a built in adjustable group latencybetween 600 μs to 1000 μs from 48 KHz to 384 KHz, so the requirement forthe input signal perspective may be met. As shown in FIG. 1, the inputsignal is sent both to the interpolator 100 and the Class G controlcircuit 400. Therefore, while the input signal is processed and delayedin the interpolator 100, the Class G control circuit 400 detects thesignal amplitude and controls the buck charge pump 502, as needed, to bein the correct mode for that input signal amplitude. That is, the ClassG Control circuit 400 looks ahead at the incoming signal to adjust themode of the buck charge pump 502 as needed and allow the buck chargepump 502 voltage to settle before the signal is received at the Class Gamplifier 200.

There are four inputs to the Class G control circuit 400, an inputsample of two channels and an ANC 300 output of two channels. The outputof the Class G control circuit 400 has four bits: two for mode control,one for transition and one for increase. FIG. 10 shows a state diagramfor controlling the buck charge pump 502. At start up, the buck chargepump 502 starts in mode 00. It stays at mode 00 for t_transition timeperiod plus t_static time period before beginning a transition to mode01.

At the beginning of each transition, the transition bit is set to highand the increase bit is set to 0 or 1 depending on an increase ordecrease in mode. The mode bits are set to the new mode. The transitionbit and increase bit hold their value for t_transition time period.After that time period, both bits go to 0. When a high signal isdetected, i.e., a signal level above a threshold, a countdown starts forincreasing the mode. At the end of the countdown, a new transitionbegins, as needed. A countdown for decreasing the mode starts as long asthe signal is below a threshold. If the signal is above the threshold,the countdown restarts. If the countdown reaches its end, a newtransition begins as needed.

The countdowns and thresholds for increasing and decreasing areprogrammable. The time intervals are 8 bit values with units of 48 KHzsample period. The threshold constants depend on mode and are also 8 bitvalues with unit 2⁻⁸ full scale.

There are two counters (not shown) for the transition time and thecountdown time. The counters are managed as discussed in detail above.One register bit is used to indicate the detection of a large signal andfor waiting for mode increase. The controller 404 can program themaximal mode and the minimal mode. Further, an enable bit may be set bythe controller 404 so the mode stays in the maximal mode and neverchanges.

The main components of the counters are two 20 bit counters,approximately 15 adders, and approximately 10 comparators. Therefore,the amount of hardware is limited. Further, the current is also verysmall. The total number of flip flops is less than 100. The clock ratecan be as low as 384 KHz. The current consumption then should be lessthan 0.1 mA.

To avoid clipping when the audio signal increases across a modethreshold level, the audio signal should be buffered sufficiently toallow the buck charge pump 502 to reach the new level before the audioincreases. For example, as discussed above, the audio input signal isbuffered in the interpolator 100. For a decreasing transition, the modemay be changed immediately, but the signal must remain below thethreshold of the new Class G mode long enough to return to the higherinitial mode.

FIGS. 11-16 show the timing constraints for several of the possibleClass G mode transitions as the envelope of the audio signal changes.FIG. 11 shows an abrupt increase in amplitude across one threshold. Ascan be seen in FIG. 11, the sw_gmode signal goes high for t_transitiontime period to allow the buck charge pump 502 to change modes for theupcoming signal envelope. The buck charge pump 502 is then in the newmode when the signal with the increased amplitude is received.

FIG. 12 illustrates an abrupt increase in amplitude across twothresholds. Again, the sw_gmode signal goes high to initiate thetransition of modes for the buck charge pump 502. In FIG. 12, it can beseen that the signal envelop is greater than in FIG. 11, so twotransitions are required for the buck charge pump 502. That is, sw_gmodegoes high for a t_transition time period to allow for a mode change, islow during the t_static time period, and then goes high again for at_transition time period to allow for another mode change prior to thesignal envelope going high.

FIG. 13 illustrates an abrupt increase in amplitude across onethreshold, then an abrupt decrease. As can be seen in FIG. 13, sw_gmodeagain goes high to initiate the transition. Sw_gmode stays high for thet_transition period to change modes, and then goes low for the t_statictime period. However, the signal envelope then has an abrupt decrease,so the sw_gmode goes high again for a t_transition period, which is lessthan the first t_transition period, for the mode to decrease. It takesless time for the mode to decrease than increase, so the secondt_transition period is smaller than the first t_transition period.

FIG. 14 illustrates an abrupt decrease in amplitude across onethreshold. Similar to FIG. 11, sw_gmode goes high to start thetransition. However, in FIG. 14, the signal envelope has decreased, theso the t_transition time period is shorter to allow the buck charge pump502 to decrease in modes.

FIG. 15 illustrates an abrupt decrease in amplitude across twothresholds. Similar to FIG. 12, sw_gmode goes high to start thetransition. Here, there is a large decrease in the signal envelope, sothe buck charge pump 502 must change through two transitions.

FIG. 16 illustrates an abrupt decrease in amplitude across onethreshold, then an abrupt increase, so there is no change in the mode.That is, the decrease counter above never reached its end before theamplitude increase, so the mode did not change.

As mentioned above, the Class G control circuit 400 includes a lowdropout voltage regulator 402, a controller 404, a comparator (notshown) to determine when the buck charge pump 402 has reached thedesired value on falling transitions, and a non-overlap clock generator406 to generate clock signals for both the buck charge pump 502 andcharge pump inverter 504.

The low dropout linear voltage regulator 402 creates a local 1.2V supplyfor digital processing. The pup_ldo_hpreg level shifter shown in FIG. 3is enabled by the pwrup signal, while all other level shifters areenabled by the output of the pup_hpreg level shift. The default statefor all logic signals is zero, so the Class G control circuit 400 isinitialized in the default logic state when pup_hpreg goes high.

The controller 404 is a semi-synchronous state machine for providing thegraceful mode transitions of the buck converter 502. During initialpower up of the converters and when increasing the supply voltage forthe Class G operation, an eight bit shift register is used in thecontroller 404 to provide decreasing resistance of the switches 202connected to the line supply. The resistance starts at a large valueupon start up or a mode transition and is reduced at 16 μs intervalsuntil the minimum switch resistance is selected. This feature limits theline current to reasonable values as the fly and hold capacitors 204reach the desired voltage levels.

When reducing the supply voltage during Class G operation, the buckconverter 502 clock is halted in the discharge state until the buckcharge pump 502 output reaches the desired state. This reduces the linecurrent to a low value and eliminates current from being injected backto the accessory power.

The controller 404 has a variety of different functions. One suchfunction is a soft start enable feature that immediately startsswitching with a high switch resistance to minimize surge current fromthe input line power since excessive stress on the input line power maydisrupt system behavior. The buck charge pump 502 naturally draws alarge current in startup and the soft start feature provides a moreefficient method of powering the buck charge pump 502 at startup.

A synchronous divide by sixteen is used to provide the soft start andmode transition resistance intervals. The clock divider is clocked withthe negative edge of the 1 MHz reference clock to provide at least 500ns margin for all logic transitions. All flip flops are reset if thesoft start feature is unused.

The soft start enable signals, en_soft_up and en_soft_dn, shown in FIG.3, are static controls. The Class G direction signal gdir is provided bythe controller 404 to indicate the direction of the transition of thebuck converter 502 output VDDHP. Table 2 below shows the status of thesoft start feature based on the en_soft_up and en_soft_dn signals.

TABLE 2 en_soft_up en_soft_dn Soft Start Feature 0 0 Unused 0 1 Noeffect when increasing, eliminates negative line current when decreasing1 0 Reduces surge current when increasing, no effect when decreasing 1 1Reduces surge current when increasing, eliminates negative line currentwhen decreasing

The synchronizer (not shown) of the controller 404 acquires a positivechange of sw_gmode, the signal which initiates a class G modetransition, as discussed above. Two flip flops triggered on the positiveedge of the 1 MHz clock are used to prevent metastability. A third flipflop synchronizes the mode transition to the positive edge of the divideby sixteen clock mentioned above, which rises on the negative edge ofthe 1 MHz clock. The ldzb (load zero bar) signal goes low at least 500ns before the synchronized rising edge of the divided clock and returnshigh immediately after the rising edge of the divided clock. This signalinitializes the state machine for increasing Class G transitions.

The controller 404 also includes a shift register to generate 16 μsintervals for controlling the resistance of the switches 202 in the buckconverter 502. The outputs of the generator are low to indicate higherresistance and are high for reduced resistance. All signals aresynchronized to the divided clock. The soft start feature is enabled ifen_soft is high.

The controller 404 also includes a function to disable the buckconverter 502 non overlap clock during decreasing Class G transitions.Disabling the buck non-overlap clock 406 is synchronized with thedivided clock which occurs on the negative edge of the clklm signal.This is when the converters in the buck charge pump 502 are switching tothe discharging phase ϕ2, so the buck charge pump 502 is disconnectedfrom the line. This prevents current from being injected back into theline as the hold capacitor is discharged. Since the hold capacitorsupplies the positive headphone amplifier current as the supply voltagesdrop and the quiescent current of the buck switch drivers is eliminated,maximum efficiency is achieved.

When the output of the buck charge pump 502 VDDHP reaches the desiredlevel, the signal VDDHP_lo goes high. On the next positive edge of theclklm signal, the buck non-overlap clock 406 is re-enabled and theconverter switches to the charging phase ϕ1.

The non-overlap clock signal for the buck charge pump 502 from thenon-overlap clock 406 is disabled in mode 00 until a synchronized softstart is enabled in mode 01. The inverter non-overlap clock signal fromthe non-overlap clock 406 continues to run throughout the negative ClassG transition while the buck converter non-overlap clock is disabled.This allows the charge pump inverter 504 to continue to track the buckconverter 502 during the mode transition.

If the soft start feature is enabled, the Class G mode transition issynchronized with the resistance reduction signals and the 1 MHz clock.If soft start is disabled, the Class G mode control signals bypass theflip flops of the resistance reduction signals.

The comparator (not shown) of the Class G control circuit 400 indicateswhen the output of the buck converter 502, VDDHP, has reached thedesired level. The reference is a three to one divider from VDDHP whenin 3:1 mode and a two to one divider otherwise. The output of thecomparator is high if VDDHP is above the reference. The charge pumpinverter 504 translates the logic to 1.2V and a high at vddhp_loindicates that the buck converter 502 output VDDHP is below the desiredvalue.

The Class G control circuit 400 also includes a ripple counter (notshown) with a selectable output to provide 1/1, 1/2, 1/4, and 1/8 clockrates to the non-overlap generator 406. The clock divider should beconfigured to divide by 1 MHz during start up and Class G modetransitions. The lower clock rates are provided to reduce quiescentcurrent during standby with no load, or for low load applications suchas line out.

The non-overlap clock generator 406 of the Class G control circuit 400controls the charge phases ϕ1 and ϕ2.

The non-overlap clock generator 406 includes a programmable delay cellto set the non overlap time. A simple non-inverting multiplexer isprovided for choosing the desired delay tap. Both the input and outputof the delay cell are buffered to minimize linearity errors because ofunit-to-unit loading. With double buffering, the unit cell isnon-inverting and simplifies the programmable delay cell.

Returning to FIG. 1, as discussed above, the latency of the interpolator100 provides enough lead time for the Class G control circuit 400 topredict the signal level at the amplitude and increase the Class Gregulator 500 mode to avoid clipping. However, when the ANC 300 is used,as shown in FIG. 1, the input signal is processed with very little delayso there is not enough time for the Class G regulator 500 to transitionto the required mode.

The Class G control circuit 400 has two amplitude inputs: the audioinput and the ANC output. Ideally, the ANC output signal is a delayedsignal plus the ANC generated signal noise. If latency is notconsidered, the ANC output signal, or just adding the ANC generatedsignal, is enough latency for the Class G control circuit 400. Becauseof latency, the future ANC noise values must be estimated.

The Class G control circuit 400 supports four modes: (1) a mode when ANCgenerated signal noise is ignored and only the input signal is used forcontrol; (2) a mode when current noise value only, where the inputsignal+noise*C is used for control and C is the ANC margin constant; (3)a mode when only noise peak is used, where the input signal+the noisepeak*C is used for control, where C is the ANC margin constant and noisepeak is the maximal noise amplitude since the last peak reset; and (4) acombined current noise and peak, when the input signal+the noise*C+noisepeak is used for control.

If ANC 300 is not active, the first mode is chosen. If ANC 300 isactive, for a typical environment, mode 2 would suffice. To performthese modes, the controller 404 includes peak registers to keep themaximal noise value since the last peak reset, the input signal peak andthe ANC output signal peak. All three modes are readable by the Class Gcontrol circuit 400 for debugging and calibration purposes.

The ANC output signal is not used for the Class G control, but is usedto trigger Class G interrupts. If the ANC output signal is more than ¾of the full scale and the Class G mode is not 2, or the ANC outputsignal is more than ½ of the full scale and the Class G mode is not 1,overflow interrupt is generated.

FIG. 17 illustrates the non-overlap clock generator 406 circuit includedin the Class G control circuit 400. The clock is normally 1 MHz but maybe programmed down for power reduction. The clock is generated in thedigital system and must be glitch-free to avoid unpredictable effects inthe Class G regulator 400 circuitry. FIG. 17 shows a functional diagramof selecting one of 6 possible clock frequencies in the glitchlessmultiplexer 1700, although a programmable frequency divider may also beused.

By default, the HP_CLK_OVERRIDE_EN inputted into multiplexer 1702 ishigh and the Class G regulator 500 frequency is determined by the valuein the HP_CLK_OVERRIDE register, and by default the frequency is 1 MHz.When HP_CLK_OVERRIDE_EN is false, then the frequency is a function ofthe Class G operating mode. Associate with each of the four Class Goperating modes is a 3 bit HP_CLK_CMx register that selects the Class Gregulator 500 frequency for the 4 HP_CLK frequency registers.

By default, HP_CLK_EN is low and is set high to enable the Class Gregulator 500.

Although the above discussed embodiments discuss the Class G controlsystem with respect to a headphone system, the disclosed technology isnot limited to such a system. The Class G control system above may beused with any Class G amplifier for any type of system to provide moreefficient power supply to the Class G amplifier.

The previously described versions of the disclosed subject matter havemany advantages that were either described or would be apparent to aperson of ordinary skill. Even so, all of these advantages or featuresare not required in all versions of the disclosed apparatus, systems, ormethods.

Additionally, this written description makes reference to particularfeatures. It is to be understood that the disclosure in thisspecification includes all possible combinations of those particularfeatures. For example, where a particular feature is disclosed in thecontext of a particular aspect or embodiment, that feature can also beused, to the extent possible, in the context of other aspects andembodiments.

Also, when reference is made in this application to a method having twoor more defined steps or operations, the defined steps or operations canbe carried out in any order or simultaneously, unless the contextexcludes those possibilities.

Furthermore, the term “comprises” and its grammatical equivalents areused in this disclosure to mean that other components, features, steps,processes, operations, etc. are optionally present. For example, anarticle “comprising” or “which comprises” components A, B, and C cancontain only components A, B, and C, or it can contain components A, B,and C along with one or more other components.

Also, directions such as “right” and “left” are used for convenience andin reference to the diagrams provided in figures. But the disclosedsubject matter may have a number of orientations in actual use or indifferent implementations. Thus, a feature that is vertical, horizontal,to the right, or to the left in the figures may not have that sameorientation or direction in all implementations.

Although specific embodiments of the invention have been illustrated anddescribed for purposes of illustration, it will be understood thatvarious modifications may be made without departing from the spirit andscope of the invention. Accordingly, the invention should not be limitedexcept as by the appended claims.

1. A power supply to provide power to an electrical device, comprising:an amplifier having multiple power rails and configured to providedifferent power supply voltages at the multiple power rails; aninterpolator configured to receive a first audio input signal; an activenoise cancellation circuit configured to receive a second audio inputsignal and an output signal from the interpolator; a control circuitconfigured to receive the first audio input signal and an output signalfrom the active noise cancellation circuit and determine the powersupply voltages to be provided by the amplifier at the multiple powerrails based on the first audio input signal and the output signal fromthe active noise cancellation circuit; and a voltage regulatorconfigured to receive an output signal from the control circuit andproduce the power supply voltages for the amplifier based on thereceived output signal.
 2. The power supply of claim 1 furthercomprising a summer configured to mix the output signal from theinterpolator with the output signal from the active noise cancellationcircuit.
 3. The power supply of claim 1 further comprising adigital-to-analog converter configured to receive an output from thevoltage regulator and provide the determined power supply voltages tothe amplifier based on the received output.
 4. The power supply of claim1 wherein the control circuit is configured to determine the powersupply voltages based on an amplitude of the second audio input signal.5. The power supply of claim 1 wherein the voltage regulator includes amulti-mode buck charge pump.
 6. The power supply of claim 5 wherein thevoltage regulator further includes an inverting charge pump.
 7. Thepower supply of claim 6 in which the control circuit is furtherconfigured to determine whether a soft start up is enabled.
 8. The powersupply of claim 7 in which the control circuit is further configured tomodify a switching resistance of switches in the buck charge pump basedon a determination that the soft start up is enabled.
 9. The powersupply of claim 1 in which the voltage regulator is a digital regulator.10. The power supply of claim 1 in which the voltage regulator is aconfigurable discrete regulator.
 11. The power supply of claim 1 inwhich the amplifier is a class G amplifier.
 12. A circuit to determinevoltages to be provided to an amplifier having multiple power rails, thecircuit comprising: an interpolator configured to receive a first audioinput signal; an active noise cancellation circuit configured to receivea second audio input signal and an output signal from the interpolator;a control circuit configured to receive the first audio input signal andan output signal from the active noise cancellation circuit anddetermine the power supply voltages to be provided by the amplifier atthe multiple power rails based on the first audio input signal and theoutput signal from the active noise cancellation circuit; and aregulator device configured to receive an output signal from the controlcircuit and produce the power supply voltages for the amplifier based onthe output signal from the control circuit.
 13. The circuit of claim 12further comprising a digital-to-analog converter configured to receivean output from the regulator device and provide the determined powersupply voltages to the amplifier based on the received output.
 14. Amethod for providing voltages to an amplifier, comprising: receiving afirst audio input signal by an interpolator and a control circuit;receiving a second audio input signal by the active noise cancellationcircuit; determining by a control circuit a selectable pair of powersupply voltages for multiple power rails of the amplifier based on thefirst audio input signal and an output signal from the active noisecancellation circuit; receiving an output signal from the controlcircuit by a regulator device; and producing the selectable pair ofpower supply voltages by the regulator device based on the receivedoutput signal.
 15. The method of claim 14 further comprising generatinga delayed audio input signal by the interpolator and passing it to theactive noise cancellation circuit.
 16. The method of claim 15 in whichthe determining by the control circuit is further based on the delayedaudio input signal.
 17. The method of claim 14 wherein determining theselectable pair of power supply voltages is based on an amplitude of thesecond audio input signal.
 18. The method of claim 14 further comprisingdetermining whether a soft start up is enabled by the control circuit.19. The method of claim 18 further comprising modifying a switchingresistance of switches in a buck charge pump of the regulator devicebased on a determination that the soft start up is enabled.
 20. Themethod of claim 18 further comprising switching between the power supplyvoltages based on a configuration of the amplifier.